MC912D60ACPVE8 Datasheet, PDF (297/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Freescale Interconnect Bus
SCI0/MI Bus registers
SC0BDH and SC0BDL are considered together as a 16-bit baud rate
control register.
Read any time. Write SBR[12:0] anytime. Low order byte must be written
for change to take effect. Write SBR[15:13] only in special modes.
The value in SBR[12:0] determines the clock rate of the MI Bus. The
desired baud rate is determined by the following formula:
MI BUS Clock Rate = _{1--M-6----C-×}----L-B---K-R---
BR is the value written to bits SBR[12:0] to establish baud rate.
NOTE:
The baud rate generator is disabled until TE or RE bit in SC0CR2
register is set for the first time after reset, and/or the baud rate generator
is disabled when SBR[12:0] = 0.
BTST — Reserved for test function
BSPL — Reserved for test function
BRLD — Reserved for test function
Bit 7
6
5
4
3
2
1
Bit 0
—
WOMS
—
—
—
—
—
PT
RESET:
0
0
0
0
0
0
0
0
SC0CR1 — MI Bus Control Register 1
$00C2
Read or write anytime.
WOMS — Wired-Or Mode for Serial Pins
This bit controls the two pins (TxD0 and RxD0) associated with the
SC0 section.
0 = Pins operate in a normal mode with both high and low drive
capability.
1 = Each pin operates in an open drain fashion if that pin is
declared as an output.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Freescale Interconnect Bus
Technical Data
297