AMD-761 Datasheet, PDF (99/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–21 Reserved
20
Function
Reserved
Reserved
GART/AGP Mode Control (Dev0:F0:0xB0)
19 NonGART_Snoop NonGART Snoop
When set, this bit forces AGP accesses that are not in the GART range to cause
AMD Athlon™ processor system bus probes to the processor(s). When clear, AGP
addresses that fall outside of the GART range do not cause probes.
18
Reserved
17 PDC_En
16 Lv1_Index
15–0 Reserved
Programming Notes
Gart Page Directory Cache Enable
This bit is used only in the two-level GART mode. It has no effect in the one-level GART
mode. The GART directory is enabled only when both this bit and the AGP Features
Control register (offset 02h of the memory-mapped Features and Capabilities register—see
“Bar1 + 0x00” on page 141) bit 2, "GART Cache Enable", are 1s.
Level 1 Index (GART Index Scheme Control)
When set to 1, this bit enables the one-level GART mode. When cleared to 0, two-level
GART mode is enabled.
Reserved
Chapter 2
AMD-761™ System Controller Programmer’s Interface
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