AMD-761 Datasheet, PDF (139/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
AGP/PCI Status, I/O Base and Limit
31
30
29
28
27
Bit
PERR_Rcv
SERR_Rcv
Mas_ABRT
Trgt_ABRT
Trgt_ABRTS
_Signaled
Reset
0
0
0
0
0
R/W
R
R/W1C
23
22
Bit Fast_B2B
UDF
Reset
0
0
R/W
21
20
19
66M
Cap_Lst
1
0
0
R
15
14
13
12
11
Bit
IO_Lim[15:12]
Reset
0
0
0
0
0
R/W
R/W
7
6
5
4
3
Bit
IO_Base[15:12]
Reset
0
0
0
0
0
R/W
R/W
Dev1:0x1C
26
25
24
DEVSEL_Timing
Data_PERR
0
1
0
R
18
17
16
Reserved
0
0
0
10
9
8
IO_Lim_R
0
0
1
R
2
1
0
IO_Base_R
0
0
1
R
Register Description
The Secondary Status register reflects the conditions of the secondary PCI-to-PCI bridge interface (the AGP bus). The I/O
Base register defines the bottom (inclusive) of an address range that is used by the bridge to determine when to forward
I/O transactions from one interface to the other. The I/O Limit register defines the top (inclusive) of an address range that
is used by the bridge to determine when to forward I/O transactions from one interface to the other.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
127