AMD-761 Datasheet, PDF (213/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
CPU
Producer
Northbridge
FLAG
DATA
Data Posted in Northbridge
PCI Bus
PCI Agent
Consumer
• Producer (CPU) writes data to the agent (consumer), data is
posted in the bridge posting buffer.
• Producer sets flag in memory.
• Consumer reads flag, causing the posting buffer to be auto-
matically flushed with ordering rules compliance enabled.
Figure 6. Example of System with Flag and Data Stored across PCI Bus Domain
5.1.3
Special Arbitration Considerations for the Southbridge
To accommodate legacy DMA as is supported in the AMD-766™
peripheral bus controller (the devices connected to the
AMD-761 system controller’s SBREQ# and SBGNT# pins), the
AMD-761 system controller makes special exceptions in the
arbitration for the Southbridge.
„ The Southbridge is not preempted or disconnected when it
gains access to the PCI bus as a master. This design prevents
potential deadlock conditions that can occur with legacy
DMA. There are no BIOS requirements to enable or disable
this functionality.
„ Before winning bus arbitration, the AMD-761 system
controller’s internal memory read and write queues can
optionally be locked and flushed. This option is controlled
by the SB_Lock_Dis bit in the PCI Arbitration Control
register (Dev 0:F0:0x84, bit 8). This bit is cleared for normal
operation.
Chapter 5
PCI Bus Interface
201