AMD-761 Datasheet, PDF (14/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
1.1 General BIOS Initialization Requirements
The following sections provide general requirements for BIOS
w h e n p ro g ra m m i n g t h e A M D -7 6 1 s y s t e m c o n t ro l l e r
configuration registers. Note that the register descriptions also
include some specific programming notes.
1.1.1
AMD-761™ Configuration Spaces
The AMD-761 system controller contains both I/O and memory-
mapped configuration spaces as listed below.
„ I/O Mapped Space
• PCI configuration space address and data (CF8h, CFCh)
• Host bridge registers mapped in PCI configuration
space, device 0, function 0
• DDR interface PDL and I/O controls mapped in PCI
configuration space to device 0, function 1
• PCI to PCI bridge/AGP registers mapped in PCI
configuration space to device 1, function 0
„ GART Memory-Mapped Registers
• Mapped in memory space as defined by the
programming of Base Address 1: GART Memory Mapped
Register Base
1.1.2
Special Configuration Sequencing Requirements
This section outlines a few cases in the AMD-761 system
controller configuration registers that require special handling
for proper BIOS programming.
Configuration Cycles
Enable
The AMD-761 system controller supports configuration
address space as defined by the PCI Local Bus Specification,
Revision 2.2, which defines a unique 256-byte space that is
accessed through two 32-bit index registers mapped in I/O
space.
As defined in the PCI specification, configuration cycles are
generated on the PCI bus only when bit 31 of the Configuration
Address register is set.
2
Overview
Chapter 1