AMD-761 Datasheet, PDF (182/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
data from the check bit storage of the DIMMs. If the generated
value does not match the check bit value, then both values are
used to detect the number of bits that contain errors and the
bit positions that contain errors. If only a single-bit error is
detected, the generated check bits and the read check bits are
used to correct the bit and pass the corrected data back to the
requester that requested the read data. This single-bit error is
signalled for system status. A read requester may be either the
AMD Athlon™ processor, PCI, AGP, APC, or GART. The
detection of more than a single-bit error signals a multiple-bit
system error and this data is not corrected. When any of the
AMD-761 system controller ECC features are enabled, all DDR
DIMMs installed must support ECC and all memory locations
must be written to (initialized) prior to system operation to
generate check bit values that match the data written for every
location of memory. It is the responsibility of the BIOS to
initialize all memory locations prior to any ECC function being
enabled.
The additional logic to support the ECC function is costly in
both silicon real estate and system timing. In the ECC modes
that support data correction, one additional system clock must
be used to generate the corrected data. However, because the
AMD Athlon processor checks for its own errors, data is passed
directly through the AMD-761 system controller without an
additional system clock delay.
The detailed implementation of error detection and correction
differs dependent on whether the read or write is from the
processor or PCI, APC, AGP, or GART and whether the write is
a full quadword or less than a full quadword in size. The
processor generates ECC for all full quadword writes and
checks and corrects (if necessary) on all reads. For processor,
PCI, APC, AGP, or GART partial quadword writes, the memory
system performs a read-modify-write operation by reading the
existing memory location, correcting the memory data if
necessary, merging in the modified bytes, generating new ECC,
and writing the new value to memory. A read-modify-write
operation is used only for all partial quadword writes. The data
read from memory during a read-modify-write operation is
checked and corrected before the merge/write operation. A
detailed operation is further described in Table 29 on
page 171.
170
DDR SDRAM Interface
Chapter 3