AMD-761 Datasheet, PDF (208/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Table 32. AMD-761™ Processor System Controller PCI Read Transaction Options
PCI_DT_En
PCI_OR_En
Tgt_Latency
Dev 0:F0:0x4C, bit 2 Dev 0:F0:0x4C, bit 1 Dev 0:F0:0x84, bit 23
Description
0
Disabled
0
Disabled
0
Disabled
No PCI transaction ordering or target latency
rules are enforced. Delayed transactions are
disabled, but masters are not retried by the
AMD-761™ system controller during memory
reads (unless the PCI_WR_Post_Rty bit is set in
the PCI Arbitration Register at Dev 0:F0:0x84).
This mode is not fully PCI 2.2-compliant
because the AMD-761 system controller host
bridge may consume greater than 32 PCI bus
clocks during memory read transactions, and
transaction ordering is not strictly enforced.
1
Enabled
0
Disabled
1
Enabled
Delayed transactions are enabled and target
latency rules are enforced. This mode is not
fully PCI 2.2-compliant because transaction
ordering rules are not strictly enforced.
1
Enabled
1
Enabled
1
Enabled
Delayed transactions are enabled, target latency
and transaction ordering rules are enforced. This
mode provides full PCI 2.2-compliance.
The effects of the settings described in Table 32 above are
described further in the following sections.
5.1.1
Delayed Transactions and Target Latency
Delayed transactions and read target latency should be
enabled and disabled together in the AMD-761 system
controller, such that both bits are either set or cleared.
„ Setting the read target latency bit (Tgt_Latency) forces the
AMD-761 system controller to disconnect the current PCI
memory read cycle in progress when the defined maximum
allowable latency has expired. This latency is defined in the
PCI Local Bus Specification, Revision 2.2, as 16 PCI clocks (32
PCI clocks for host bridges that must snoop processor
caches). When the read target latency is reached, the
AMD-761 system controller asserts the STOP# signal, thus
disconnecting the PCI master (retry). The master is then
obligated by protocol to retry the same cycle after re-
arbitration, in anticipation that the read has completed in
the memory subsystem, thus the next read cycle falls within
the maximum target latency.
„ Setting the delayed transaction enable (PCI_DT_En) causes
the AMD-761 system controller to latch the address and
read command that was initiated by the external master
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PCI Bus Interface
Chapter 5