AMD-761 Datasheet, PDF (138/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions
Bit Name
31–24 Secon_Lat_Timer
23–16 Sub-Bus_Num
15–8 Secon_Bus_Num
7–0 Pri_Bus_Num
AGP/PCI Sub Bus Number/Secondary Latency Timer (Dev1:0x18)
Function
Secondary Latency Timer
Adheres to the definition of the latency timer in the PCI Local Bus Specification, Revision
2.2, but only applies to the secondary interface of a PCI-to-PCI bridge.
Sub-Bus Number
This bit field records the number of the highest numbered PCI bus that is behind (or
subordinate to) a bridge. The bridge uses this number in conjunction with the Secondary
Bus Number register to determine when to respond to type 1 configuration transactions
on the primary interface and to pass them on to the secondary interface.
Secondary Bus Number
This bit field records the number of the PCI bus that the secondary interface of the bridge
is connected to. The bridge uses this number to determine when to respond to type 1
configuration transactions on the primary interface and to convert them to type 0
transactions on the secondary interface.
Primary Bus Number
This bit field records the number of the PCI bus that the primary interface of the bridge is
connected to. The bridge uses this number to decode type 1 configuration transactions on
the secondary interface that should be converted to special cycle transactions on the
primary interface.
Programming Notes
The AGP bus is logically a sub-bus of the PCI bus. The PCI bus normally enumerates as bus 0 and the AGP bus
enumerates as bus 1.
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AMD-761™ System Controller Programmer’s Interface
Chapter 2