AMD-761 Datasheet, PDF (160/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions
Bit Name
31–12 GART_Tbl_Entry
_Addr
11–2 Reserved
1 Tbl_Update
0 Tbl_Inval_Entry
GART Table Cache Entry Control (Bar1 + 0x10)
Function
GART Table Entry Address
These bits define the page address for the particular GART table entry to be invalidated or
updated. When a page address is written to this register by the AMD-761™ miniport
driver, the referenced GART table cache entry is invalidated or updated based on the value
in bits [1:0] as long as it is within the virtual address space. If the page address is outside of
the virtual address space, then the invalidate/update instructions do nothing.
Reserved
Table Update
When set, this bit forces the AMD-761 system controller to update the GART table cache
entry specified in bits [31:12] with the current entry in the GART table in system memory.
The update function is performed immediately following the write to this register. When
the update operation is completed, this bit is reset to 0.
Table Invalidate Entry
When set, this bit forces the AMD-761 system controller to invalidate the GART table cache
entry specified in bits [31:12] if it is present in the GART cache. The invalidate function is
performed immediately following the write to this register. When the invalidate operation
is completed, this bit is reset to 0. Note that this bit does not affect the GART
directory cache.
Programming Notes
148
AMD-761™ System Controller Programmer’s Interface
Chapter 2