AMD-761 Datasheet, PDF (212/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
With Ordering Rules
Disabled
4. The PCI master regains bus ownership and attempts to read
the flag again. This time it successfully reads the flag and
the previously posted write data has already been written to
the master’s target interface.
It should be noted that this configuration is rare, as most
systems place the data and the flag in main memory.
Using Figure 6 as an example, the following case describes the
behavior of the AMD-761 system controller when ordering
rules are not followed.
1. The processor writes data (memory write) destined to an
agent on the PCI bus, and the data is posted in the AMD-761
system controller PCI posting buffer.
2. The processor then sets a flag in memory, informing the PCI
agent that the data is written.
3. The PCI master reads the flag, but the associated data
(previously written by the processor) has not been flushed
from the AMD-761 system controller posted write buffer.
This situation results in a data incoherency.
Again, as in the case when ordering rules are enabled, note
that this configuration is rare, as most systems place the data
and the flag in main memory. The AMD-761 system controller
provides the ordering rules feature for compliance to the PCI
Local Bus Specification, Revision 2.2.
200
PCI Bus Interface
Chapter 5