AMD-761 Datasheet, PDF (154/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions
Bit Name
31–30 Reserved
29–28 Valid_Bit_Err_ID
27 P2P_Status
26 GART_Cache
_Status
25 Reserved
24 Valid_Err
23–20 Reserved
19 P2P_En
18 TLB_En
17 SB_STB_Tog
_Det_Dis
16 GAR_Valid_Err
_En
15–12 Reserved
11 Hang_En
Features and Capabilities (Bar1 + 0x00)
Function
Reserved
Valid Bit Error ID
These bits are used to determine the source of the valid bit error. The values are as follow:
00 = AGP
01 = CPU
10 = PCI/AGP’s PCI
11 = Reserved
P2P Status
This bit is hardwired to 0 to indicate that the AMD-761™ system controller implements
only those PCI-to-PCI bridge commands required to implement AGP (the AMD-761 system
controller does not implement a complete PCI 2.1-compliant PCI-to-PCI bridge between
PCI and AGP).
GART Cache Status
0 = GART cache disabled
1 = GART cache enabled by software
Reserved
Valid Bit Error
When set, this bit indicates that a valid bit error has been detected and SERR# has been
asserted. Refer to Table 7 on page 34 for details about SERR# assertion and status. This bit
is cleared by writing a 1.
Reserved
P2P Enable
This bit is hardwired to 0 to indicate that the AMD-761 system controller only implements
those PCI-to-PCI bridge commands required to implement AGP (the AMD-761 system
controller does not implement a complete PCI 2.1-compliant PCI-to-PCI bridge between
PCI and AGP).
TLB Enable
When set, this bit enables the caching of GART TLB entries.
Sideband Strobe Toggle Detect Disable
When set, this bit disables the AGP sideband strobe toggle detect logic.
GART Valid Error Enable
When set, the AMD-761 system controller asserts SERR# when a graphics device attempts
to access a page in AGP memory that is not valid (valid bit error). A valid bit error causes
the GART table walk state machine to hang. The processor can still access memory after
that if it does not use GART address space. Refer to Table 7 on page 34 for details about
SERR# assertion and status.
Reserved
Hang Enable
When set, illegal GART entries fetched by the GTW logic forces the AMD-761 system
controller to hang.
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AMD-761™ System Controller Programmer’s Interface
Chapter 2