AMD-761 Datasheet, PDF (249/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Registers
-----
Bits
Description
Initialized/
Required
Value
Actual
Value
Key
fcn( )
Notes
0x0x1x40h DDR PDL Calibration Control
31:8 Reserved
0000_000h
SW_Recal
7
0b
Set after setting SW_Cal_Dly
6
Use_Act_Dly
0b
Use Actual Delay
1b
Auto_Cal_En
5
Auto Calibration Mode
4
Act_Dly_Inh
0b
Actual Delay Update Inhibit
3:2
Reserved
00b
Auto_Cal_Period
1:0
Auto-Calibration Period
01b
r
Write 1=>Calibration
B
0=Calibration Complete
1=Calibration Not Complete
0=Disable,
B
1=Enable SW_Recal and
Auto_Cal_En Must = 0
When Use_Act_Dly = 1
0=Disable
1=Enable
B
Refer to AMD-761™ System
Controller Revision Guide,
order# 23613, for special
instructions for Revision B2
silicon.
0=Disable
1=Enable
B
Refer to AMD-761™ System
Controller Revision Guide,
order# 23613, for special
instructions for Revision B2
silicon.
r
00=10000 System Clocks
01=1000000 System Clocks
B
10=10000000 System Clocks
11=Reserved
0x0x1x44h DDR PDL Configuration Register 0
31:24 Clk_Dly
yyh
23:16 SW_Cal_Dly
xxh
15:8 Cal_Dly
yyh
7:0
Act_Dly
xxh
c
Half Period of the System Clock
Delay for DQS:
100 MHz = 69h
B FSB _{133 MHz = 6Bh}
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or Direct Write
KEY:
B= Mandatory BIOS function
A= AGP setup by BIOS
c = Calculated/set by AMD-761™ internal logic
P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS
r = Hardcoded and reserved
u = PCI operational user interface E = Elective BIOS function
Chapter 7
Recommended BIOS Settings
237