AMD-761 Datasheet, PDF (85/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions (Continued)
PCI Arbitration Control (Dev0:F0:0x84)
Bit Name
Function
3 Tgt_Lat_Tim_ Target Latency Timer Disable
Dis
When the AMD-761™ system controller acts as a PCI target, it has a latency timer that
retries the (write) cycle if it cannot respond within 8 bus clocks (16 clocks for the first
transfer). When set, this bit disables the AMD-761 system controller’s target latency timer
on both the standard PCI and AGP PCI interfaces.
Note: To prevent potential deadlocks caused by PCI to AGP traffic on the system, this
bit should be cleared and bit 23 (Tgt_Latency) must be set. Note also that
setting this bit disables the Tgt_Latency function controlled by bit 23.
2 AGP_Pref_En AGP Prefetch Enable
When set, this bit enables the AMD-761 system controller to prefetch data from the
SDRAM when a PCI master on the standard AGP bus reads from the main memory.
1 PCI_Pref_En
PCI Prefetch Enable
When set, this bit enables the AMD-761 system controller to prefetch data from the
SDRAM when a PCI master on the PCI bus reads from the main memory.
0 Park_PCI
Park PCI
When set, this bit enables parking on an external PCI master. When clear, the PCI arbiter
only parks on processor accesses to PCI.
Programming Notes
To avoid potential deadlocks for systems that use traffic from the PCI bus to the PCI bus of the AGP, clear the write target
latency timer disable bit (bit 3, Tgt_Lat_Tim_Dis), and set the read target latency timer bit (bit 23, Tgt_Latency). Refer to
the programming notes for the PCI Control register (Dev 0:F0:0x4C) for details on the recommended setting of the
Tgt_Latency bit.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
73