AMD-761 Datasheet, PDF (145/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Definitions
Bit Name
31–20 Prefet_Mem_Lim
19–16 Reserved
15–4 Prefet_Mem_Base
3–0 Reserved
AGP/PCI Prefetchable Memory Limit and Base (Dev1:0x24)
Function
Prefetchable Memory Limit Address
Prefetchable memory limit address defines the top address of the prefetchable address
range used by the AGP target (graphics controller) where control registers and FIFO-like
communication interfaces are mapped. The lower 20 bits of address are assumed to be
0xFFFFF. The memory address range adheres to 1-Mbyte alignment and granularity.
Reserved
Prefetchable Memory Base Address
Prefetchable memory base address defines the base address of the prefetchable address
range used by the AGP target (graphics controller) where control registers and FIFO-like
communication interfaces are mapped. Bits [15:4] correspond to address bits [31:20]. The
lower 20 bits of the address are assumed to be 0. The memory address range adheres to
1-Mbyte alignment and granularity.
Reserved
Programming Notes
Chapter 2
AMD-761™ System Controller Programmer’s Interface
133