AMD-761 Datasheet, PDF (17/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Table 1. AMD-761™ System Controller Configuration Register Bits Unknown at RESET#
Register Name
ECC Mode/Status
DRAM Timing
DRAM Mode/Status
Status/Control
Memory Base Address 0–7
Offset
Dev 0:F0:0x48
Dev 0:F0:0x54
Dev 0:F0:0x58
Dev 0:F0:0x70
Dev 0:F0:0xC0
through
Dev 0:F0:0xDC
Bit Name
SERR_Enable
ECC_Diag
ECC_Mode
SBPWaitState
Addr_Timing_A
Addr_Timing_A
RD_Wait_State
Reg_DIMM_En
t_WTR
t_WR
t_RRD
Idle_Cyc_Limit
PH_Limit
t_RC
t_RP
t_RAS
t_CL
t_RCD
Burst_Ref_En
Ref_Dis
Reserved
Cyc_Per_Ref
CS7_X4Mode
CS6_X4Mode
CS5_X4Mode
CS4_X4Mode
CS3_X4Mode
CS2_X4Mode
CS1_X4Mode
CS0_X4Mode
Self_Ref_En
CS_Base
CS_Mask
Addr_Mode
CS_En
Bit(s)
[15:14]
[12]
[11:10]
[31]
[30]
[29]
[28]
[27]
[26]
[25:24]
[23]
[18:16]
[15:14]
[11:9]
[8:7]
[6:4]
[3:2]
[1:0]
[20]
[19]
[18]
[17:16]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[18]
[31:23]
[15:7]
[2:1]
[0]
Chapter 1
Overview
5