AMD-761 Datasheet, PDF (214/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
5.2
5.2.1
By default, the AMD-761 system controller does not allow the
SBREQ# PCI request to be preempted by requests on the
normal REQ#[6:0] pins, and it does not disconnect the
Southbridge once it has started a transfer.
PCI Performance Optimization Options
In addition to transaction level options as listed in Section 5.1
on page 195, the AMD-761 system controller PCI bus interface
provides various system level options that can be used to tune
the system performance. Each of these options are described in
the following sections.
Read Prefetching
When the AMD-761 system controller is the target of PCI
memory read accesses to system memory, the AMD-761 system
controller’s PCI target interface initiates a probe of the
AMD Athlon™ processor’s cache and a read of eight quadwords
(a single cache line) from memory. Setting the read prefetching
bit (PCI_Pref_En, Dev 0:F0:0x84, bit 1) causes the AMD-761
system controller to prefetch another eight quadwords from
memory, speculating that the PCI master will request another
cache line at the next cache-aligned address.
The obvious advantage to read prefetching is that masters that
are reading multiple contiguous cache lines of data can stream
this data more effectively on the PCI bus. The disadvantage is
that it could result in wasted bandwidth of the memory
subsystem of the prefetched data that is purged because it was
not needed by the PCI master.
202
PCI Bus Interface
Chapter 5