AMD-761 Datasheet, PDF (140/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions
Bit Name
31 PERR_Rcv
30 SERR_Rcv
29 Mas_ABRT
28 Trgt_ABRT
27 Trgt_ABRTS
_Signaled
26–25 DEVSEL_Timing
24 Data_PERR
23 Fast_B2B
22 UDF
21 66M
20 Cap_Lst
19–16 Reserved
15–12 IO_Lim[15:12]
11–8 IO_Lim_R
AGP/PCI Status, I/O Base and Limit (Dev1:0x1C)
Function
Detected Parity Error
This bit is always Low because the AMD-761™ system controller does not support
parity checking.
Signaled System Error
This bit is set whenever the AMD-761 system controller received AGP SERR#. This bit is
cleared by writing a 1. Refer to Table 7 on page 34 for details about SERR# assertion
and status.
Received Master Abort
This bit is set by the AMD-761 system controller whenever a bus master transaction
(except for a special cycle) is terminated due to a master abort. This bit is cleared by
writing a 1.
Receive Target Abort
This bit is set by the AMD-761 system controller whenever a bus master transaction (except
for a special cycle) is terminated due to a target abort. This bit is cleared by writing a 1.
Signaled Target Abort
This bit is always 0 because the AMD-761 system controller does not terminate
transactions with target aborts.
DEVSEL# Timing
This field is always 0x1, indicating that the AMD-761 system controller supports medium
DEVSEL# timing.
Data PERR#
This bit is always 0 because the AMD-761 system controller does not report data
parity errors.
Fast Back-to-Back Capable
This bit is always 0, indicating that the AMD-761 system controller as a target is not
capable of accepting fast back-to-back transactions when the transactions are not to the
same agent.
User-Definable Features
This bit is always 0, indicating that UDF is not supported on the AMD-761 system
controller.
66-MHz Capable
This bit is always 1, indicating that the AMD-761 system controller supports 66 MHz on
device 1.
Capabilities List
This bit is always 0, indicating that the configuration space of this device does not support
a capabilities list.
Reserved
I/O Limit (Write)
This bit field indicates the upper writable 4 bits that define the top address of an address
range that is used by the bridge to determine when to forward I/O transactions from one
interface to the other.
I/O Limit (Read)
The lower read-only 4 bits define the top address of an address range that is used by the
bridge to determine when to forward I/O transactions from one interface to the other. 0x1
indicates that 32-bit I/O address decoding is available.
128
AMD-761™ System Controller Programmer’s Interface
Chapter 2