AMD-761 Datasheet, PDF (16/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Interrupt Pin Control
R/W Attributes
Silicon Revisions
The AMD-761 system controller provides BIOS the ability to
override the reporting of fast write and 4X rate support. This
override function is accomplished through a write to a separate
register, which is required because the AGP Status register is
specified as read-only in the AGP specification.
Refer to Section 6.2 on page 208 for details of this
implementation.
The Int_Pin field in the AGP/PCI Interrupt and Bridge Control
register (Dev 1:F0:0x3C) is read-only by default and initializes
to all 0s. If the BIOS is required to initialize this field to
another value, it must first change this field to R/W by setting
the Int_Pin_Cntl bit in the Miscellaneous Device 1 Control
register (Dev 1:F0:0x40).
The AMD-761 system controller does not use the Int_Pin field
internally, the register is provided for software compatibility only.
The reader is advised to read the AMD-761™ System Controller
Revision Guide, order# 23613, for the most current information
for the version of silicon being used. The silicon revision is
available by reading the PCI revision ID and Class Code
register in Dev 0:F0:0x08.
1.1.3
Power-On Reset Initialization
All of the AMD-761 system controller’s configuration registers
must be initialized by BIOS after initial power-on, paying especially
close attention to the registers that are not initialized to a known
value.
T h e A M D -7 6 1 s y s t e m c o n t r o l l e r i s re s e t w h e n t h e
Southbridge’s PCIRST# pin is asserted, which occurs when
transitioning from the Mechanical Off, S5, S4, or S3 sleep
states.
To accommodate support of the Advanced Configuration and
Power Interface (ACPI) S3 (suspend to RAM) power
management state, the registers listed in Table 1 on page 5 are
not initialized to a known state after reset (RESET# asserted),
and they must be initialized by BIOS after initial power-on for
proper operation. These registers retain the value programmed
by BIOS after subsequent assertions of the RESET# pin when
transitioning to and from the S3 sleep state.
4
Overview
Chapter 1