AMD-761 Datasheet, PDF (61/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
AMD Athlon™ Processor System Bus Dynamic Compensation
31
30
29
28
27
26
Bit
Reserved
Reset
0
0
0
0
0
0
R/W
R
Dev0:F0:0x50
25
24
0
0
23
22
21
20
19
18
17
16
Bit
PVal
NVal
Reset
0
0
0
0
0
0
0
0
R/W
R
15
14
13
12
11
10
9
8
Bit
BYP_P
BYP_N
Reset
0
0
0
0
0
0
0
0
R/W
R/W
7
6
5
4
3
2
1
0
Bit
SlewCntl
BYP
Reserved
Reset
0
1
1
0
0
0
0
0
R/W
R/W
R/W
R
Register Description
Note that the default value of the BYP, BYP_P, and BYP_N fields of this register can be optionally controlled by SIP bits
when loading the SIP stream from external ROM.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
49