AMD-761 Datasheet, PDF (203/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
„ Self-refresh must be enabled by writing a 1 to the
Self_Ref_En bit in the Status/Control register (Dev
0:F0:0x70, bit 18).
„ To ensure that no probes are generated, all PCI/AGP traffic
must be prevented by the peripheral software drivers before
entering the S3 state when DCSTOP# is asserted. It is
expected that the drivers have already placed each PCI/AGP
peripheral into the D3 state prior to STPCLK# assertion by
the Southbridge.
„ The Suspend to RAM control bits (STR_Control[1:0]) in the
DRAM Mode/Status register (Dev 0:F0:0x58) must be
properly controlled by BIOS to force the AMD-761 system
controller to properly enter and exit the S3 state. Refer to
Section 4.4.1 on page 191 for details.
To accommodate S3 support, the AMD-761 system controller
does not initialize most of the memory controller configuration
registers to a known value when RESET# is asserted. It is
important that these registers be properly initialized by BIOS
during the power-up configuration. Once initialized, the
AMD-761 system controller retains these values when
resuming from the S3 state.
4.4.1
STR Bit Control for S3 Support
The STR_Control bits are provided to allow BIOS to
communicate state changes to the AMD-761 system controller’s
power management logic. Proper control of these bits is
required to ensure that the correct sequence is followed when
the AMD-761 system controller is entering and exiting the
Suspend to RAM state.
Each of the three STR_Control modes are described below.
Power-On Reset (00)
The AMD-761 system controller always sets the STR_Control
bits to this value when the RESET# pin is asserted—that is,
when powering up from the S3, S4, S5, and Mechanical Off
states). The AMD-761 system controller memory controller
always drives the DRAM CKE pins Low in this state, forcing
the DRAMs inactive, and the memory controller configuration
registers retain the values they had prior to the RESET#
assertion.
Chapter 4
Power Management
191