AMD-761 Datasheet, PDF (250/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Registers
-----
Bits
Description
Initialized/
Required
Value
Actual
Value
Key
fcn( )
Notes
0x0x1x48h DDR PDL Configuration Register 1
31:24 Clk_Dly
yyh
23:16 SW_Cal_Dly
xxh
15:8 Cal_Dly
yyh
7:0
Act_Dly
xxh
c
Half Period of the System Clock
Delay for DQS:
100 MHz = 69h
B FSB
133 MHz = 6Bh
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or Direct Write
0x0x1x4Ch DDR PDL Configuration Register 2
31:24 Clk_Dly
yyh
23:16 SW_Cal_Dly
xxh
15:8 Cal_Dly
yyh
7:0
Act_Dly
xxh
c
Half Period of the System Clock
Delay for DQS:
B FSB ^{100 MHz = 69h}
133 MHz = 6Bh
c
SW_Cal_Dly in # of Buffers
c
from SW_Recal or Direct Write
0x0x1x50h DDR PDL Configuration Register 3
31:24 Clk_Dly
yyh
23:16 SW_Cal_Dly
xxh
15:8 Cal_Dly
yyh
7:0
Act_Dly
xxh
c
Half Period of the System
Clock
Delay for DQS:
100 MHz = 69h
B FSB
133 MHz = 6Bh
c
SW_Cal_Dly in # of Buffers
c
from SW_Recal or Direct Write
0x0x1x54h DDR PDL Configuration Register 4
31:24 Clk_Dly
yyh
23:16 SW_Cal_Dly
xxh
15:8 Cal_Dly
yyh
7:0
Act_Dly
xxh
c
Half Period of the System
Clock
Delay for DQS:
100 MHz = 69h
B FSB _{133 MHz = 6Bh}
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or Direct Write
0x0x1x58h DDR PDL Configuration Register 5
31:24 Clk_Dly
yyh
23:16 SW_Cal_Dly
xxh
15:8 Cal_Dly
yyh
7:0
Act_Dly
xxh
c
Half Period of the System Clock
Delay for DQS:
100 MHz = 69h
B FSB
133 MHz = 6Bh
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or Direct Write
KEY:
B= Mandatory BIOS function
A= AGP setup by BIOS
c = Calculated/set by AMD-761™ internal logic
P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS
r = Hardcoded and reserved
u = PCI operational user interface E = Elective BIOS function
238
Recommended BIOS Settings
Chapter 7