AMD-761 Datasheet, PDF (174/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Idle Cycle Limit
Registered DIMM
Enable
adequate to give fair access to the memory sub-system.
Therefore, these bits should be set to 10b. A higher page hit
limit allows the prioritization of a large amount of consecutive
page hits, if available, whereas a lower page hit limit would
allow for a greater chance of page interruption should there be
an otherwise large amount of page hit requests. Refer to
Table 27 on page 165 for typical settings.
The Idle Cycle Limit bits (Dev 0:F0:0x54, bits [18:16]) specify
the number of system clocks before the memory controller
issues a PRECHARGE ALL command to the currently active
chip select. This feature is used to tune system performance by
closing open pages during periods of memory request
inactivity. The idle cycle limit logic does not have any logical
indication of page conflicts or bank misses and simply counts
the number of system clocks of memory request inactivity. This
feature takes advantage of the lack of temporal locality, where
a page left open for a specified amount of time is less likely to
be accessed again. Therefore, it is more advantageous to
precharge the page and incur the page miss overhead rather
than the overhead associated with a page conflict.
Analysis shows that eight idle clocks is an adequate amount of
system clocks to wait for a following request to the memory
sub-system. Therefore, these bits should be set to 001b for best
performance. A higher idle cycle limit allows a greater chance
for a following request to access an open page. However,
temporal locality states that the greater amount of time
between accesses reduces the chance of a hit to the open page.
A lower idle cycle limit decreases the window of following
memory access to utilize an open page. A lower idle cycle limit
results in a greater chance of page interruption should there be
an otherwise large amount of page hit requests. Refer to
Table 27 on page 165 for typical settings.
The Registered DIMM Enable bit (Dev 0:F0:0x54, bits [27])
specifies whether the DDR DIMM sockets are populated with
registered or unbuffered DIMM modules. This bit is set to 1b
by BIOS if the DIMM sockets are populated with DDR-
re g i s t e re d D I M M m o d u l e s . Th e A M D -7 6 1 s y s t e m
controllerAMD-761 system controller memory controller does
not support the mixing of registered and unbuffered DDR
modules in the same system. The system must be populated
162
DDR SDRAM Interface
Chapter 3