AMD-761 Datasheet, PDF (71/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions (Continued)
DRAM Mode/Status (Dev0:F0:0x58)
Bit Name
Function
17—16 Cyc_Per_Ref
Cycles Per Refresh
Refresh counter defines period of refresh requests.
The following table shows the relationship between the values in this field and the
resultant refresh period for the different system clock frequencies:
Value
00
01
10
11
66 MHz
30.72 µs
23.04 µs
15.36 µs
7.68 µs
100 MHz
20.48 µs
15.36 µs
10.24 µs
7.68 µs
133 MHz
15.36 µs
11.52 µs
7.68 µs
3.84 µs
15–8 Reserved
7 CS7_X4Mode
6 CS6_X4Mode
5 CS5_X4Mode
4 CS4_X4Mode
3 CS3_X4Mode
2 CS2_X4Mode
1 CS1_X4Mode
0 CS0_X4Mode
Reserved
Chip-Select 7 X4Mode Enable
0 = This chip select consists of non-x4 devices (disabled).
1 = This chip select consists of x4 devices (enabled).
Chip-Select 6 X4Mode Enable
0 = This chip select consists of non-x4 devices (disabled).
1 = This chip select consists of x4 devices (enabled).
Chip-Select 5 X4Mode Enable
0 = This chip select consists of non-x4 devices (disabled).
1 = This chip select consists of x4 devices (enabled).
Chip-Select 4 X4Mode Enable
0 = This chip select consists of non-x4 devices (disabled).
1 = This chip select consists of x4 devices (enabled).
Chip-Select 3 X4Mode Enable
0 = This chip select consists of non-x4 devices (disabled).
1 = This chip select consists of x4 devices (enabled).
Chip-Select 2 X4Mode Enable
0 = This chip select consists of non-x4 devices (disabled).
1 = This chip select consists of x4 devices (enabled).
Chip-Select 1 X4Mode Enable
0 = This chip select consists of non-x4 devices (disabled).
1 = This chip select consists of x4 devices (enabled).
Chip-Select 0 X4Mode Enable
0 = This chip select consists of non-x4 devices (disabled).
1 = This chip select consists of x4 devices (enabled).
Chapter 2
AMD-761™ System Controller Programmer’s Interface
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