AMD-761 Datasheet, PDF (48/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
PCI Latency Timer and Header Type
Dev0:F0:0x0C
31
30
29
28
27
26
25
24
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
23
22
21
20
19
18
17
16
Bit
Header_Type
Reset
0
0
0
0
0
0
0
0
R/W
R
15
14
13
12
11
10
9
8
Bit
Lat_Timer
Reset
0
0
0
0
0
0
0
0
R/W
R/W
7
6
5
4
3
2
1
0
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
Register Description
Bit Definitions
Bit Name
31–24 Reserved
23–16 Header_Type
15–8 Lat_Timer
7–0 Reserved
Programming Notes
PCI Latency Timer and Header type (Dev0:F0:0x0C)
Function
Reserved
Header Type
Bit 23 is always 0, indicating that the AMD-761™ system controller is a single function device.
Bits [22:16] are 0, indicating that Type 00 configuration space header format is supported.
Latency Timer
This bit field defines the minimum amount of time in PCI clock cycles that the bus master
can retain ownership of the bus. This action is mandatory for masters that are capable of
performing a burst consisting of more than two data phases.
Reserved
36
AMD-761™ System Controller Programmer’s Interface
Chapter 2