AMD-761 Datasheet, PDF (167/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
This document assumes that BIOS uses the SPD to determine
the total amount of memory in the system. This document does
not specify a sizing algorithm other than utilizing the SPD.
Base Address
Chip Select
The Base Address Chip Select bits (Dev 0:F0:0xC0, bits [31:23]
through Dev 0:F0:0xDF, bits [31:23]) specify the 8-Mbytes
boundary a given chip-select services. Each of the eight chip
selects [7:0] have an associated Base Address Chip Select
register. Incoming addresses are compared against the value
programmed into the Base Address Chip Select register and
also the Address Mask bits (Dev 0:F0:0xC0, bits [15:7] through
Dev 0:F0:0xDF, bits [15:7]) of this register.
Address Mask
The Address Mask bits (Dev 0:F0:0xC0, bits [15:7] through Dev
0:F0:0xDF, bits [15:7]) specify which address bits to ignore
when incoming addresses are compared to the Base Address
Chip Select bits Dev 0:F0:0xC0, bits [31:23] through Dev
0:F0:0xDF, bits [31:23]) defined in Base Address Chip Select. If
a given bit is set in this register, its corresponding address bit
in the address compare is ignored.
Address Mode
The Address Mode bits (Dev 0:F0:0xC0, bits [2:1] through Dev
0:F0:0xDF, bits [2:1]) specify the memory address mapping.
The address memory mapping is specific to the symmetry of
the device and is shown in Table 21. As can be seen in this
table, the maximum page width is 2 Kbytes. This maximum
width implies that a new internal bank is accessed on a 2-Kbyte
boundary. Note that address modes 00b and 11b are reserved,
thus this field should never be specified.
Table 21. AMD-761™ System Controller DDR SDRAM Addressing Modes
Mode
Mode 1
Addr_Mode=01
64Mb x4/8/16
128Mb x4/8/16
Mode 2
Addr_Mode=10
256Mb x4/8/16
512Mb x4/8/16
Pins 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Row ^{12 11}
24 23 22 21 20 19 18 17 16 15 14 13
Col ^{12 11}
27 PC 26 25 10 9 8 7 6 5 4 3
BK BK
Row ^{12 11 25 24 23 22 21 20 19 18 17 16 15 14 13}
Col ^{12 11 29 28 PC 27 26 10 9 8 7 6 5 4 3}
BK BK
Chapter 3
DDR SDRAM Interface
155