AMD-761 Datasheet, PDF (194/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
3.9
182
„ Once the appropriate PDL value is determined for each
byte or nibble (as it applies), this value must be converted
into a Software Calibration Delay value for the auto-
calibration logic. This value can be calculated by
multiplying the “target window PDL tap” (found above) by
the “average delay per PDL tap,” which yields the
“required PDL tap delay” as a function of time (ns).
„ The Software Calibration delay is specified as a percentage.
Therefore, the Software Calibration delay = ((operating
period/2) / required PDL tap delay) x 256). The value
determined in this calculation must be applied to the
Software Calibration Delay field Dev 0:F1:0x44, bits [23:16],
through Dev 0:F1:0x88, bits [23:16].
„ Clear the Actual Delay Update Inhibit Dev 0:F1:0x40, bit
[4] to allow calibration updates and then enable the auto-
calibration system by writing a 1b to Dev 0:F1:0x40, bit [5].
DDR I/O Drive Strength
The DDR I/O pads are SSTL-2 compatible. The DDR pads have
configurable slew rate and drive strength control of N and P
transistors, separately. It is the responsibility of BIOS to
initialize the pad drive strength and slew rate before any
memory accesses. The DDR I/O drive strength and slew
controls exist at (Dev 0:F1:0x8C) through (Dev 0:F1:0x9B).
Drive strength and slew control are provided for both the P and
N transistors to allow for a fine adjustment for proper DDR
SSTL-2 crossover points and rise/fall edge rates.
Separate drive strength and slew control is provided for the
following:
„ Data strobes (DQS)
Note: If any chip select is configured to support a x4 DIMM, the
DM buses inherit the drive strength and slew setting
specified for the data strobes (DQS). Otherwise, the DM pins
inherit the drive strength specified for the MDAT pins. This
inheritance occurs because a x4 DIMM access uses the DM
signals as data strobes (DQS) signals.
„ Data bus (MDAT), ECC bus (MECC), and data mask bus
(DM) (See preceding note.)
„ Device clock output (CLKOUTH/L)
DDR SDRAM Interface
Chapter 3