AMD-761 Datasheet, PDF (67/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions (Continued)
DRAM Timing (Dev0:F0:0x54)
Bit Name
Function
1–0 t_RCD
t_RCD
This bit field (t_RCD) is the timing value (RAS to CAS latency, delay from activate to RD/WR
command).
11 = 4 cycles
10 = 3 cycles (recommended “safe” configuration)
01 = 2 cycles
00 = 1 cycle
Programming Notes
This register is not initialized at reset. BIOS must initialize all bits in this register prior to setting the SDRAM_Init bit (See
“Bit Definitions DRAM Mode/Status (Dev0:F0:0x58)” on page 57) or attempting DRAM access for correct operation.
The required settings for the wait state bits for SBP_Wait_State and Rd_Wait_State are listed in Table 8.
Table 8. Wait State Settings for DRAM Timing Register
DDR Interface
Frequency
66 MHz
100 MHz
133 MHz
SBP_Wait_State [Bit 31]
0
0
1
Rd_Wait_State [Bit 28]
0
1
1
Chapter 2
AMD-761™ System Controller Programmer’s Interface
55