AMD-761 Datasheet, PDF (251/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Registers
-----
Bits
0x0x1x5Ch
31:24
23:16
15:8
7:0
0x0x1x60h
31:24
23:16
15:8
7:0
0x0x1x64h
31:24
23:16
15:8
7:0
0x0x1x68h
31:24
23:16
15:8
7:0
0x0x1x6Ch
31:24
23:16
15:8
7:0
KEY:
Description
DDR PDL Configuration Register 6
Clk_Dly
Initialized/
Required Actual
Value Value
yyh
SW_Cal_Dly
xxh
Cal_Dly
yyh
Act_Dly
xxh
DDR PDL Configuration Register 7
Clk_Dly
yyh
SW_Cal_Dly
xxh
Cal_Dly
yyh
Act_Dly
xxh
DDR PDL Configuration Register 8
Clk_Dly
yyh
SW_Cal_Dly
xxh
Cal_Dly
yyh
Act_Dly
xxh
DDR PDL Configuration Register 9
Clk_Dly
yyh
SW_Cal_Dly
xxh
Cal_Dly
yyh
Act_Dly
xxh
DDR PDL Configuration Register 10
Clk_Dly
yyh
SW_Cal_Dly
xxh
Cal_Dly
yyh
Act_Dly
xxh
B= Mandatory BIOS function
A= AGP setup by BIOS
P= Power management setup by BIOS o = Setup by OS or OS driver
r = Hardcoded and reserved
u = PCI operational user interface
Key fcn( )
Notes
c
Half Period of the Sys. Clk.
Delay for DQS:
B
FSB
100 MHz = 69h
133 MHz = 6Bh
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or
Direct Write
c
Half Period of the Sys. Clk.
Delay for DQS:
B FSB ^{100 MHz = 69h}
133 MHz = 6Bh
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or
Direct Write
c
Half Period of the Sys. Clk.
Delay for DQS:
100 MHz = 69h
B FSB
133 MHz = 6Bh
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or
Direct Write
c
Half Period of the Sys. Clk.
Delay for DQS:
100 MHz = 69h
B FSB _{133 MHz = 6Bh}
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or
Direct Write
c
Half Period of the Sys. Clk.
Delay for DQS:
B FSB ^{100 MHz = 69h}
133 MHz = 6Bh
c
SW_Cal_Dly in # of Buffers
c
From SW_Recal or
Direct Write
c = Calculated/set by AMD-761™ internal logic
F = Performance enhancement set by BIOS
E = Elective BIOS function
Chapter 7
Recommended BIOS Settings
239