AMD-761 Datasheet, PDF (15/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Function 1 Space
Memory-Mapped
BARs
Memory Holes
AGP Override Bits
for 4X Rate
and Fast Writes
The configuration registers that control the memory interface’s
Programmable Delay Lines (PDLs) and I/O drive strengths are
mapped to device 0: function 1 in the host bridge. This
configuration space is disabled by default and requires a write
to the PCI Control register’s Func1_En (Dev 0:F0:0x4C, bit 0).
The intent of this separate configuration space is that it is
configured at initial power-on, subsequently disabled, and
essentially protected from further writes.
„ Note that the AMD-761 system controller does not report as
a multifunction device (bit 7 is not set in the Header_Type
field in the PCI Latency Timer and Header Type register in
Dev 0:F0:0x0C).
„ Reads to the PCI header that normally occupies offsets 00h–
3Fh return all 1s—that is, the normal PCI header registers
are not implemented.
Five DWORD registers are accessed by the AMD-761 system
controller AGP miniport driver as memory-mapped space. This
space is defined by the Base Address 1: GART Memory-
Mapped Register Base (Dev 0:F0:0x14), which provides address
bits [31:12] of the memory-mapped space. Note that this space
is defined as a 4-Kbyte region, hence the lower address bits
[11:4] are 0s.
This register must be properly programmed by BIOS to allow
the driver to access the memory-mapped space.
Legacy memory holes are decoded in the normal region of main
memory from 640 Kbyte to 1 Mbyte. The AMD-761 system
controller does not allow PCI masters to access DRAM in this
region unless the EV6_Mode bit is set in the PCI Arbitration
Control Register. See “Bit Definitions PCI Arbitration Control
(Dev0:F0:0x84)” on page 71.
The AGP Status register (Dev 0:F0:0xA4) reports the AMD-761
system controller’s capability to support AGP fast writes and
the AGP-4X rate. The operating system normally reads these
bits along with the same bits in the AGP card’s status register,
and uses this information to configure the AGP Command
register (Dev 0:F0:0xA8) in the AMD-761 system controller and
the AGP card.
Chapter 1
Overview
3