AMD-761 Datasheet, PDF (125/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions (Continued)
DDR CMDB/CMDA Pad Configuration (Dev0:F1:0x94)
Bit Name
Function
13–11 PSlewCMDA
Command A Rising Edge Slew Rate
These bits control the rising edge slew rate of the RASA#, CASA#, WEA#, and CKEA# pins.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
10–8 NSlewCMDA
Command A Falling Edge Slew Rate
These bits control the falling edge slew rate of the RASA#, CASA#, WEA#, and
CKEA# pins.
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
7–4 Reserved
Reserved
3–2 PDrvCMDA
Command A P Transistor Drive Strength
These bits control the P transistor drive strength of the RASA#, CASA#, WEA#, and
CKEA# pins.
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
1–0 NDrvCMDA
Command A N Transistor Drive Strength
These bits control the N transistor drive strength of the RASA#, CASA#, WEA#, and
CKEA# pins.
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
Programming Notes
Chapter 2
AMD-761™ System Controller Programmer’s Interface
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