AMD-761 Datasheet, PDF (232/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Registers
-----
Bits
Description
Initialized/
Required
value
Actual
Value
Key
fcn( )
Notes
0x0x0x58h SDRAM Mode/Status
31
Clk_Dis5 – DIMM Clock 5
xb
30
Clk_Dis4 – DIMM Clock 4
xb
29
Clk_Dis3 – DIMM Clock 3
xb
28
Clk_Dis2 – DIMM Clock 2
xb
27
Clk_Dis1 – DIMM Clock 1
xb
26
Clk_Dis0 – DIMM Clock 0
xb
25
SDRAM Init
1b
24
Reserved
0b
23
Mode register status
xb
22:21
STR_Control = Suspend to
RAM Control
xxb
20
Burst refresh enable
0b
19
Ref_Dis = Refresh Disable
0b
18
Reserved
0b
Cycles per (between) Refresh
17:16
SPD # 12
xxb
15:8
0_0h
E MB 0=Enable, 1=Disable
E MB 0=Enable, 1=Disable
E MB 0=Enable, 1=Disable
E MB 0=Enable, 1=Disable
E MB 0=Enable, 1=Disable
E MB 0=Enable, 1=Disable
Set to start memory
controller.
B
All other memory config bits
should be set before setting
this bit. Stays set, can be
reset but not to 0.
r
To be set before or with
SDRAM Init. Causes writing
of the memory mode
B
register when SDRAM Init is
set. After setting, drops to 0
when function complete.
Cannot be set to 0.
Set <---> Last Power State
01b <---> MOFF, S4 or S5
B
10b <---> S3
Refer to “S3 Suspend to
RAM State Requirements”
on page 190 for details.
B
0-Disable, 1-Enable
B
1 = Disable Refresh = Debug Bit
B
@100 MHz FSB:
00 = 2K cyc, 01 = 1.5K cyc
FSB
10 = 1K cyc, 11 = 0.75K cyc
B and _{@133-MHz FSB:}
SPD
00=1.5K cyc, 01=1.1K cyc
10=0.75K cyc, 11=0.37K cyc
r
KEY:
B= Mandatory BIOS function
A= AGP setup by BIOS
c = Calculated/set by AMD-761™ internal logic
P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS
r = Hardcoded and reserved
u = PCI operational user interface E = Elective BIOS function
220
Recommended BIOS Settings
Chapter 7