AMD-761 Datasheet, PDF (171/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
t_RCD
t_RAS
t_RP
t_RC
t_RRD
Chapter 3
The RAS to CAS delay bits (Dev 0:F0:0x54, bits [1:0]) specify
the minimum amount of time required between the opening of
a page within the DDR device (via an ACTIVATE command)
and the issuance of a READ or WRITE command to that same
DDR device’s internal bank. This timing parameter is device-
specific. Byte 29 of the SPD defines the t_RCD timing parameter.
Refer to Table 25 on page 160 for typical settings.
The Row Active bits (Dev 0:F0:0x54, bits [6:4]) specify the
minimum amount of time that a page within the DDR device
(via an ACTIVATE command) can remain opened within the
same internal bank of the DDR device. This timing parameter
is device-specific. Byte 30 of the SPD defines the t_RAS timing
parameter. Refer to Table 25 on page 160 for typical settings.
The Row Precharge time bits (Dev 0:F0:0x54, bits [8:7]) specify
the minimum amount of time that the DDR device requires to
precharge a row and is specified as the time between the
PRECHARGE command and an ACTIVATE command within
the same internal bank of the DDR device. This timing
parameter is DDR device-specific. Byte 27 of the SPD defines
the t_RP timing parameter. Refer to Table 25 on page 160 for
typical settings.
The Row Cycle time bits (Dev 0:F0:0x54, bits [11:9]) specify the
minimum amount of time that the DDR device requires
between ACTIVATE commands within the same internal bank
of the DDR device. This timing parameter is DDR device-
specific. In short, this requirement specifies the minimum
amount of time that the same internal bank can recycle row
accesses. Byte 41 of the SPD defines the t_RC timing parameter.
(Note that t_RC is new to the SPD and voted in at the September
2000 JEDEC meeting.) Historically, t_RC was defined as t_RAS +
t_RP, but this algorithm is not recommended when the SPD
information is available. Refer to Table 25 on page 160 for
typical settings.
The Bank to Bank ACTIVATE time bit (Dev 0:F0:0x54, bit [23])
specifies the minimum amount of time that the same DDR
device can receive back-to-back ACTIVATE commands, even to
different internal banks. This timing parameter is DDR device-
specific. Device manufacturers specify the t_RRD parameter to
limit current surges within the device, based on row ACTIVATE
activity, because row activates require a large amount of
DDR SDRAM Interface
159