AMD-761 Datasheet, PDF (118/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions (Continued)
DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C)
Bit Name
Function
17–16 NDrvMDAT
MDAT N Transistor Drive Strength
These bits control the N transistor drive strength of the MDAT[63:0] and DM[8:0] pins.
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
Note that the DM[8:0] pins are controlled by the NDrvDQS field when any chip select is
configured for x4 DIMMs in the DRAM Mode/Status register (Dev 0:F0:0x58).
15–14 Reserved
Reserved
13–11 PSlewDQS
DQS Rising Edge Slew Rate
These bits control the rising edge slew rate of the DQS[8:0] pins (and DM[8:0] pins) when
any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at
Dev 0:F0:0x58).
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
10–8 NSlewDQS
DQS Falling Edge Slew Rate
These bits control the falling edge slew rate of the DQS[8:0] pins (and DM[8:0] pins) when
any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at
Dev 0:F0:0x58).
000 = Slew rate 0 (slowest)
001 = Slew rate 1
010 = Slew rate 2
011 = Slew rate 3
100 = Slew rate 4
101 = Slew rate 5
110 = Slew rate 6
111 = Slew rate 7 (fastest)
7–4 Reserved
Reserved
106
AMD-761™ System Controller Programmer’s Interface
Chapter 2