AMD-761 Datasheet, PDF (187/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Chapter 3
AMD-761 system controller implements a Programmable Delay
Line (PDL) to adjust the incoming DQS.
Each PDL is composed of a selectable buffer chain that is used
to delay the incoming DQS strobe for placing the DQS within
the valid data window. A separate PDL is implemented for each
DQS pin (nine total in non-x4Mode) with additional PDLs (for a
total of 18 in x4Mode) placed on the input of the data mask
(DM) pins for use when accessing a x4 DIMM. The PDL is only
used for read data capture. Because the propagation delay of
an individual buffer of the PDL is a function of process, voltage
and temperature (PVT), a mechanism is required to
compensate for these three variables. This calibration
mechanism determines the appropriate delay to apply across
PVT. A calibration mechanism is placed near every two PDLs to
accurately sense PVT near the actual PDLs used to delay the
incoming DQS strobes. Each calibration mechanism is hand
placed within the AMD-761 system controller to match gate for
gate the actual PDL. This approach minimizes error between
the calibration mechanism and the actual PDLs.
The range of each PDL is from 1 ns to 2.5 ns (worst case). The
resolution of the PDL is equal to one buffer delay inside the
AMD-761 system controller. That is, the value in the PDL
register that controls the “tap” point of the PDL delay chain
represents the number of internal buffer propagation delays.
Because the propagation delay of an internal buffer can vary
over PVT, the number of buffers (and therefore the value in the
PDL control register) can be different at different times (and
different across the same AMD-761 system controller device or
even different across selected AMD-761 system controller
devices), but it can still represent the same delay value in time
units.
Board effects (signal skews, cross talk, etc.) are incorporated in
the timing budget analysis, and they combine to reduce the
effective data-valid window width presented to the AMD-761
system controller. The PDL hardware assumes that the effects
are symmetric—that is, they shrink the setup and hold times
equally. If this symmetry is not the case for the system, then
the AMD-761 system controller allows the BIOS to compensate
for these effects.
The internally delayed DQS (output of the PDL) is used inside
the AMD-761 system controller to capture the corresponding
DDR SDRAM Interface
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