AMD-761 Datasheet, PDF (261/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Registers
-----
Bits
Description
0x1x0x1Ch PCI Command and Status
31
PERR_Rcv
30
SERR_Rcv
29
28
27
26:25
24
23
22
21
20
19:16
Master ABRT
Target ABRT
Target ABRTS Signaled
DEVSEL_Timing
Data_PERR
FastB2B
UDF
66M
Cap_Lst
Reserved
15:12 IO_Lim[15:12]
11:8 IOLimit_R
7:4
IOBase [15:12]
3:0
IOBase_R
Initialized/
Required
Value
0b
yb
yb
yb
0b
01b
0b
0b
0b
1b
0b
0h
xh
1h
xh
1h
Actual
Value
Key fcn( )
Notes
r
Not supported
u
R/W/1C from AMD-761™
system controller
u
R/W/1C from bus master
u
R/W/1c from bus master target
r
Not supported
r
r
r
r
r
r
r
Upper 4 bits defining top
address that is used by the
B
bridge to forward I/O
transactions from one
interface to another.
Lower 4 bits defining top
address that is used by the
bridge to forward I/O
r
transactions from one
interface to another. 0x1
indicates that 32 bit I/O
address decoding is available
Writable 4 bits that defines
bottom address that is used
B
by the bridge to forward I/O
transactions from one
interface to another.
Lower 4 bits defining bottom
address that is used by the
bridge to forward I/O
r
transactions from one
interface to another. 0x1
indicates that 32 bit I/O
address decoding is available.
KEY:
B= Mandatory BIOS function
A= AGP setup by BIOS
c = Calculated/set by AMD-761™ internal logic
P= Power management setup by BIOS o = Setup by OS or OS driver F = Performance enhancement set by BIOS
r = Hardcoded and reserved
u = PCI operational user interface E = Elective BIOS function
Chapter 7
Recommended BIOS Settings
249