AMD-761 Datasheet, PDF (79/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–19 Reserved
18 Self_Ref_En
17–14
Memory Status/Control (Dev0:F0:0x70)
Function
Reserved
Self-Refresh Enable
This bit enables self-refresh when entering certain power management states. This bit
should normally be set, but the option to disable this function is provided to
accommodate specific DIMMs that do not correctly support the self-refresh feature. Note
that if this bit is not set, then DCSTOP# assertion (ACPI sleep states) must be inhibited.
0 = Self-refresh disabled
1 = Self-refresh enabled
Reserved
13
Reserved
12–11
10
9
8–1
0
Reserved
PCI_Pipe_En
PCI_Blk_WR_En
Reserved
Reserved
Reserved
PCI Pipe Enable
0 = All PCI transactions, from either the PCI or AGP interfaces, force the memory
controller to check for outstanding read probes with a matching block address and
stall until these probes are complete.
1 = Memory controller pipelines PCI transactions.
Setting this bit generally increases PCI throughput. This bit must be clear when the
processor is allowed to issue CleanVictimBlock commands.
PCI Block Write Enable
0 = PCI full-block writes do RID/INV probes, forcing the memory controller to wait for
probe data movement.
1 = PCI full-block writes do NOP/INV probes.
This bit must be clear when the AMD Athlon™ processor is allowed to issue
CleanVictimBlock commands.
Reserved
Reserved
Programming Notes
Note that the Self_Ref_En bit in this register is not initialized at reset time but must be initialized by BIOS for proper
operation. This action should be done prior to attempting DRAM access.
DCSTOP# assertion (ACPI S1/S3) must not be enabled if the Self_Ref_En bit is cleared.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
67