AMD-761 Datasheet, PDF (186/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
ECC_Status
ECC_CS_MED
ECC_CS_SED
the ECC status indicators. In addition, the controller also
corrects any single-bit errors in memory.
The Error Correcting Code Status bits indicate the status of the
ECC detect logic as follows:
„ 00 = No error
„ X1 = MED: Multi-bit error detect
„ 1X = SED: Single-bit error detect
The ECC status bits and corresponding failing chip-select
indicators (see bits below) are set by the first error detected of
each type (SED or MED). The AMD-761 system controller does
not log any new errors of each type or assert SERR# until
software clears the associated ECC_Status bit by writing a 1.
The Multiple Bit Error Chip Select status provides the binary
encoded chip select for the first multiple-bit error detected by
the AMD-761 system controller. The Failing ECC Chip Select is
a binary encoded field and is valid only when the ECC_Status
bits indicate a multi-bit error was detected.
The Single-Bit Error Chip Select status provides the binary
encoded chip select for the first single-bit error detected by the
AMD-761 system controller. The Failing ECC Chip Select is a
binary encoded field and is valid only when the ECC_Status
bits indicate a single-bit error was detected.
3.8 Programmable Delay Lines (PDL)
This section describes the method used to create the delays
necessary for proper DQS operation on the AMD-761 system
controller DDR interface. The configuration registers used to
control the delays are located in Device 0:Function 1. Note that
for most systems, the BIOS should simply set the values
recommended in Section 7 on page 211. The following sections
provide a detailed description of the PDL operation and the
options for BIOS configuration.
For memory reads, the DDR devices drive the DQS pins edge-
aligned with the data, and the AMD-761 system controller must
“adjust” the incoming DQS to capture the data. The adjusting
of the incoming DQS requires delaying the DQS accordingly for
each byte or nibble. Because this timing is very tight, the
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DDR SDRAM Interface
Chapter 3