AMD-761 Datasheet, PDF (55/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–11 Reserved
15–14 Reserved
10–8 P0_WrDataDly
7-4 Reserved
3 P0_2BitPF
2–0 Reserved
Extended BIU Control (Dev0:F0:0x44)
Function
Reserved
Reserved
Write Data Delay
P0_WrDataDly is the time in SYSCLK periods from the launch of a SysDC WriteData
command until the launch of the first data object by the processor. This value is a
calculated part of the SIP stream. This value is not provided in the BIU SIP register and is
thus provided here.
Reserved
Two Bit Times Per Frame Enable
This bit enables the use of the two bit time commands on the AMD Athlon™ processor
system bus. This bit must be set when connected to an AMD Athlon processor and
disabled when connected to an Alpha processor. For proper operation, BIOS must not
clear this bit once it has been set.
0 = Two-bit time commands disabled
1 = Two-bit time commands enabled (AMD Athlon processor only)
Reserved
These bits must be written with 0 (cleared) for normal operation.
Programming Notes
Chapter 2
AMD-761™ System Controller Programmer’s Interface
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