AMD-761 Datasheet, PDF (136/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
AGP/PCI Header Type
Dev1:0x0C
31
30
29
28
27
26
25
24
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
23
22
21
20
19
18
17
16
Bit
Header_Type
Reset
0
0
0
0
0
0
0
1
R/W
R
15
14
13
12
11
10
9
8
Bit
Pri_Lat_Timer
Reset
0
0
0
0
0
0
0
0
R/W
R/W
7
6
5
4
3
2
1
0
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
Register Description
Bit Definitions
Bit Name
31–24 Reserved
23–16 Header_Type
15–8 Pri_Lat_Timer
7–0 Reserved
Programming Notes
AGP/PCI Header Type (Dev1:0x0C)
Function
Reserved
Header Type
Bit 23 is always 0, indicating that the AMD-761™ system controller is a single function device.
Bits 22:16 are 0x01, indicating that type 01 configuration space header format is supported
(PCI-to-PCI bridge).
Primary Latency Timer
This latency timer is not used in the AMD-761 system controller because the primary bus
of the PCI-to-PCI bridge is internal. This register is read/write to maintain compliance with
the PCI specifications.
Reserved
124
AMD-761™ System Controller Programmer’s Interface
Chapter 2