AMD-761 Datasheet, PDF (192/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
SW_Cal_Dly
Cal_Dly
Act_Dly
the number of PDL buffer delays required to make up a 2X
SYSCLK period. This value is used to calculate the actual PDL
value. The value returned from this field divided by the clock
frequency is the average delay per tap of the PDL.
The auto-calibrator’s Software Calibration Delay (Dev
0:F1:0x44, bits [23:16] through Dev 0:F1:0x88, bits [23:16])
provides BIOS access to the overall percentage of the buffers
required, based on the total number of buffer delays shown in
the Clk_Dly field. This value is used to calculate the actual
PDL value. This value should be:
„ 69h at 100 MHz (2.0500 ns 41.0%)
„ 6Bh at 133 MHz (1.5625 ns 41.7%)
The auto-calibrator’s Calculated Delay (Dev 0:F1:0x44, bits
[15:8] through Dev 0:F1:0x88, bits [15:8]) is read-only and
provides the calculated delay based on the auto-calibrator’s
finding of Clk_Dly and the BIOS-specified SW_Cal_Dly. This
value is the final calibration value that is used for the PDL if
the Act_Dly_Inh bit (Dev 0:F1:0x40, bit [4]) is not set. If the
Act_Dly_Inh bit is set, this calculated value is not used to
update the PDLs.
The auto-calibrator’s Actual Delay (Dev 0:F1:0x44, bits [7:0]
through Dev 0:F1:0x88, bits [7:0]) directly specifies the number
of PDL taps. BIOS can manually update the PDL by writing a
PDL tap value into this register and writing a 1b to the Use
Actual Delay bit (Dev 0:F1:0x40, bit [6]). This action should
only be done when the auto-calibration logic is disabled by
writing a 0b to (Dev 0:F1:0x40, bit [5]). Manually updating the
PDL while the auto-calibration logic is enabled could result in
unpredictable system operation.
3.8.1
180
Manual PDL Window Detection
The recommended value specified in the SW_Cal_Dly field
(Dev 0:F1:0x44, bits [23:16] through Dev 0:F1:0x88, bits
[23:16]) is based on calculated round trip timing assuming
worst case AMD-761 system controller conditions, worst case
DDR DIMM device conditions, and board routing. The most
critical timing relationship during a DDR DIMM read is the
round trip data delays and the DQS/data relationship relative
to each other. Many factors affect the DQS/data relationship.
Because of these factors, BIOS itself can determine a precise
DDR SDRAM Interface
Chapter 3