AMD-761 Datasheet, PDF (56/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
ECC Mode/Status
Dev0:F0:0x48
31
30
29
28
27
26
25
24
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
23
22
21
20
19
18
17
16
Bit
Reserved
Reset
0
0
0
0
0
0
0
0
R/W
R
15
14
13
12
11
10
Bit
SERR_Enable
Reserved ECC_Diag
ECC_Mode
Reset
X
X
R/W
R/W
0
X
X
X
R
R/W
R/W
9
8
ECC_Status
0
0
R/W1C
7
6
5
4
3
2
1
0
Bit
ECC_CS_MED
ECC_CS_SED
Reset
0
0
0
0
0
0
0
0
R/W
R
R
Register Description
This register provides ECC mode control and status reporting for the DRAM system.
Note that some bits of this register are not initialized at reset time, and all bits must be initialized by BIOS for proper
operation. This action should be done prior to attempting DRAM access.
44
AMD-761™ System Controller Programmer’s Interface
Chapter 2