AMD-761 Datasheet, PDF (219/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
6.1.2
„ To force a single compensation cycle in 3.3-V signalling
mode (typically used for debug only). In this case, both the
Do_Compensate and the Comp3.3 bits should be set, and
the AGP interface must not be enabled until this bit is read
back as a 0, indicating that the compensation cycle is
complete.
If compensation bypass is selected for both the data transfer
and strobe pins (both the BYPXfer and BYPStrb bits are set in
the Compensation Bypass register) then these fields are
ignored.
Selection of 1.5- or 3.3-V AGP Signalling
The selection of the AGP signalling type (1.5 V versus 3.3 V) is
done by the AGP card via the TYPEDET# pin when it is
installed in the AGP slot. AGP cards operating in 3.3-V
signalling mode have their TYPDET# pin unconnected. Cards
operating in 1.5-V signalling mode have the pin connected to
VSS, forcing it to 0. The AMD-761 system controller latches the
value of the TYPEDET# pin at reset, and BIOS can read this
value in the Configuration Status register (Dev 0:F0:0x88,
bit 25). The allowable rates at each signalling level are shown
in Table 33 as listed in the Accelerated Graphics Port Interface
Specification, Revision 2.0.
Table 33. Allowable AGP Rate versus Signalling Level
AGP Rate
1X
2X
4X
1.5-V Signalling
Supported
Supported
Supported
3.3-V Signalling
Supported
Supported
Not Supported
Section 6.3 on page 209 describes the recommended
initialization sequence for reading this value and configuring
various AMD-761 system controller parameters accordingly.
Chapter 6
AGP Interface
207