AMD-761 Datasheet, PDF (185/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Chapter 3
provides the benefit of detecting an error but does not incur
the one clock penalty that is necessary for data correction
for data destined for the PCI or AGP. Data and ECC check
bits are still passed from the DDR devices to the
AMD Athlon processor, which performs its own data error
detection and correction. Therefore, data correction to the
AMD Athlon processor is not inhibited in this mode. This
mode provides all the benefits of parity checking with little
or no performance impact. It is useful in systems that desire
status information but not the overhead that is associated
with error correcting or scrubbing. A system can transition
between the EC_HiPerf mode, ECC_HiPerf mode, and
ECC_Scrub mode dynamically, thereby getting the desired
benefits of each mode as needed.
„ Enable ECC error checking and correction mode. Data
destined for the PCI or APCI/GART is corrected but at the
expense of one clock cycle. As always, data and ECC check
bits are still passed from the DDR devices to the
AMD Athlon processor, which performs its own data error
detection. The AMD-761 system controller provides a high-
performance ECC mode (ECC_HiPerf) that provides all the
data integrity benefits of ECC but without the overhead of
scrubbing. In this mode, ECC is written into memory during
writes (partial writes result in a RMW sequence), and
correction is performed on reads. ECC checking is
performed and the status indicators provide valid
information regarding errors. This mode is useful in systems
that need status information and data integrity but not the
overhead that is associated with scrubbing. A system can
transition between the EC_HiPerf mode, ECC_HiPerf mode,
and ECC_Scrub mode dynamically, thereby attaining the
desired benefits of each mode as needed.
„ Enable ECC_Scrub mode where error checking, data
correction, and memory scrubbing are enabled. Memory
scrubbing corrects a detected single-bit error in the DDR
memory. When a single-bit error is detected, additional
cycle overhead is associated with correcting the single-bit
error in memory. ECC with scrubbing (ECC_Scrub) mode is
the ECC mode of highest reliability. In ECC_Scrub mode,
ECC is written into memory during writes (partial writes
result in a RMW sequence), and corrected data is provided
to the PCI/APCI/GART on reads. The AMD-761 system
controller checks the ECC returned from memory and sets
DDR SDRAM Interface
173