AMD-761 Datasheet, PDF (231/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
0x0x0x54h
SDRAM Timing
100 MHz 133 MHz
SPD ns
U R UR
31
SPBWaitState
0b
1b
0 @ 100 MHz , 1 @ 133 MHz FSB
30
AddrTiming_A SPD # 21
0b 1b 0b 1b
0 @ Unbuff, 1 @ Reg DIMM
29
AddrTiming_B, SPD # 21
0b 1b 0b 1b
0 @ Unbuff, 1 @ Reg DIMM
28
RD_Wait_State
1b
1b
Must = 1
27
Reg_DIMM_En, SPD # 21
0b 1b 0b 1b
0 @ Unbuff, 1 @ Reg DIMM
26
t_WTR = Write Data In to Read CMD 1b
1b
0 = 1 Clock, 1 = 2 Clocks
25:24 t_WR = Write Recovery Time
10b
10b
00b=1 Clock, 01b=Reserved
10b=2 Clocks, 11b=3 Clocks
23
t_RRD=ActBnkAtoActBnkCMD
SPD # 28
0b
0b 3Ch 15 0 = 2 Clocks, 1 = 3 Clocks
22:19
0000b 0000b
000 = 0 cyc, 001 = 8 cyc (safe)
18:16
Idle cycle to wait before
precharging the idle bank
001b 001b
010 = 12 cyc, 011 = 16 cyc
100 = 24 cyc, 101 = 32 cyc
110 = 48 cyc, 111 = Disable
15:14
Page Hit request before a
nonPage hit
10b
10b
00 = 1 cyc, 01 = 4 cyc
10 = 8 cyc, (safe) 11 = 16 cyc
13:12
00b
00b
t_RC = Bank Cycle Time
11:9
t_RAS + t_RP
or SPD# 41(new, not yet
implemented)
000 = 3 cyc, 001 = 4 cyc
110b 41h 65
010 = 5 cyc, 011 = 6 cyc
100b
to
to to _{100 = 7 cyc, 101 = 8 cyc (safe)}
111b 46h 70
110 = 9 cyc, 111 = 10 cyc
8:7
t_RP = Precharge Time
SPD # 27
01b
00b
50h
20
00 = 3 cyc (safe), 01 = 2 cyc
10 = 1 cyc, 11 = 4 cyc
6:4
t_RAS = Minimum Bank Active
Time
011b
100b
to
2Dh
to
45
to
000 = 2 cyc, 001 = 3 cyc
010 = 4 cyc, 011 = 5 cyc
SPD # 30
100 = 6 cyc, 101 = 7 cyc (safe)
101b _32h 50 _{110 = 8 cyc, 111 = 9 cyc}
t_CL = CAS Latency
SPD # 25 (Not Available)
3:2
# 23
#9
1:0
t_RCD — RAS to CAS Latency
SPD # 29
----
----
01b
---- A0h
01b
01b 75h
00 = 3 cyc (optional on DIMM,
not recommended)
01 = 2 cyc, recommended
10 = 2.5 cyc
10b --00b-- A0h
10b
10b 75h
11 = reserved
(See 00 above.)
00 = 1 cyc, 01 = 2 cyc
01b
10b 50h 20
10 = 3 cyc (safe), 11 = 4 cyc
Chapter 7
Recommended BIOS Settings
219