AMD-761 Datasheet, PDF (204/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Normal Resume (01)
Resume from S3 (1X)
BIOS should write this value to the STR_Control bits when
resuming from the S4 (Suspend to Disk), S5 (Soft Off), or
Mechanical Off states. This action forces the AMD-761 memory
controller to follow the normal DRAM initialization sequence
as follows:
„ Assert CKE pins to enable clocks at the DRAM DIMMs
„ Perform required DRAM initialization sequence, including
writes to DRAM mode registers, etc.
The BIOS should then follow the normal initialization sequence
in this mode, including DRAM configuration and memory
sizing, etc.
After a hard reset, BIOS should set these bits to 01b and bit 25
of this register (DRAM Init) to a 1b within the same
configuration write. If this register is not set to a 01b, setting
bit 25 of this register has no effect. This pattern is written by
BIOS to inform the AMD-761 system controller memory
controller that this is a power-on reset rather than a Suspend
To RAM wakeup from reset.
BIOS should write this value to the STR_Control bits when
resuming from the S3 (Suspend to RAM) state. This action
instructs the AMD-761 system controller memory controller to
perform the proper DDR protocol to exit self-refresh but not
attempt to re-initialize the DDR DRAM devices—that is, mode
register writes, etc.). Note that this bit is ignored by the
memory controller after it exits self-refresh, until the bit is
cleared by RESET#. Problems are thus avoided when the
AMD-761 system controller periodically enters and exits self-
refresh for C2, S1 and clock throttling.
As shown in Figure 5 on page 193, when BIOS writes a 1X to the
STR_Control field upon exiting the S3 state, the AMD-761
system controller simply takes the DRAM out of self-refresh
mode. At this time all of the AMD-761 memory controller
configuration registers retain their original values programmed
prior to entry to the S3 state, thus allowing BIOS immediate
access to memory for the restoration of all other system
configuration registers and context restoration. Refer to
Section 1.1.3 on page 4 for a list of the AMD-761 system
controller configuration registers that are not set to a known
value when the RESET# pin is asserted.
192
Power Management
Chapter 4