AMD-761 Datasheet, PDF (115/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–24 Clk_Dly
23–16 SW_Cal_Dly
15–8 Cal_Dly
7–0 Act_Dly
DDR PDL Configuration Registers 0–17 (Dev0:F1:0x44–0x8B)
Function
Clock Delay
This field provides the number of buffers that amount to one half-period of the system clock.
Note:
Upon exit from self-refresh, this bit field is updated with the number of buffers
required to equal one half-period of the system clock. The value of this field
depends on the operating PVT point. This field is also updated when a
recalibration is done either due to Auto_Cal_En or SW_Recal.
Software Calibration Delay
This bit field represents the amount of delay that is required for the corresponding DQS.
The typical value is 0x69 for 100-MHz DDR operation, or 0x6B for 133 MHz. This field is
used to calculate the Cal_Dly value during exit from self-refresh, auto-calibration, and
software-initiated recalibration. This field must be configured before setting the SW_Recal
bit or the Auto_Cal_En bit, and while these bits are set, this field must not be written.
BIOS writes a desired value into this field if the default DQS delays are not the desired
DQS delays for any reason. The value written in this field should be 256 times the required
delay as a percentage of the half-period of the system clock, and then rounded off to the
nearest integer.
For example, if the desired DQS delay is 43.5 percent of the system clock’s half-period, the
value written into this field should be 0.434 x 256 = 111 (0x6F).
Note: This bit field should not be used if the system clock frequency is 66 MHz.
Calibration Delay
This bit field provides the last Cal_Dly value in number of buffers.
Note:
Upon exit from self-refresh, this bit field is updated with the number of buffers
required to equal the time specified by the SW_Cal_Dly field. The value of this
field depends on the operating PVT point. This field is also updated when a
recalibration is done either due to Auto_Cal_En or SW_Recal.
Actual Delay
This bit field provides the current Act_Dly value (in number of buffers) that is in effect for
the corresponding PDL. Software can read the current value of Act_Dly from this field.
Software can write the desired number of buffer delays into this field. Software typically
writes to this field only if auto-calibration is disabled. After writing to this field, software
should also set the Use_Act_Dly bit in the PDL Calibration Control register.
Upon writes to this field, the new value takes effect at the first available “safe” time after
the Use_Act_Dly bit is set.
Note:
Upon exit from self-refresh, this bit field is updated with the number of buffers
required to equal the time specified by the SW_Cal_Dly field. The value of this
field depends on the operating PVT point. This field is also updated when a
recalibration is done either due to Auto_Cal_En or SW_Recal (unless the
Act_Dly_Inh bit in the PDL Calibration register is set).
Note: Values written directly by software to this field are not PVT-independent, so
this field is primarily for lab and debug use.
Programming Notes
Note that these registers are not initialized at reset time, but must be initialized by BIOS for proper operation. This action
should be done prior to attempting DRAM access, and a software-initiated calibration should be forced.
Chapter 2
AMD-761™ System Controller Programmer’s Interface
103