AMD-761 Datasheet, PDF (175/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Read Wait State
Address Timing for
Copy-B
Chapter 3
with either all registered or all unbuffered DDR modules.
Refer to Table 27 on page 165 for typical settings.
The Read Wait State bit (Dev 0:F0:0x54, bits [28]) specifies
whether more time is needed in the DDR read data round trip
loop. The read data round trip loop originates at the AMD-761
system controller DDR CLK outputs and terminates at the
AMD-761 system controller internal requester logic. Because
all DDR read data is returned with its corresponding DQS
signal, read data is captured at the memory controller interface
in the DQS clock domain. This data is then held and crosses
into the core requester clock domain. However, because of the
physical DIMM placement on the motherboard, large round
trip delays the response time of the DDR devices, and
AMD-761 system controller internal delays may be long enough
that an additional wait state must be added to compensate for
the delay. When this bit is set to a 1b, the data captured in the
DQS clock domain is transferred to a register array that is
within the core logic clock domain and physically exists at the
pads of the AMD-761 system controller DDR interface. When
this bit is set to a 1b, the data is delayed to the requester by
one additional system clock period.
Because the Read Wait State bit is related to the full read data
round trip and may imply that the read data and DQS are being
returned from a far DIMM, when the Read Wait State bit is set
to 1b, one additional clock cycle is placed between READ
followed by WRITE cycles to prevent data and DQS overlap
when accessing a far DIMM for read data and followed
immediately by a write cycle.
Because of motherboard timing analysis and AMD-761 system
controller timing analysis, it is recommended that this bit be
set for 100-MHz and 133-MHz operation. Refer to Table 27 on
page 165 for typical settings.
The address timing for Copy-B bit (Dev 0:F0:0x54, bit [29])
specifies additional HOLD time for the address and command
bus B. When this bit is set to 1b, the memory address bus
(MAB[14:0]), RASB#, CASB#, WEB#, CKEB, and CS[7:6 and
3:2]# is delayed an additional 350 ps (best case) and 600 ps
(worst case) to provide additional HOLD time to the DDR
device. This bit should be set by BIOS when registered DIMMs
are installed and set to 0b when unbuffered DIMMs are
installed.
DDR SDRAM Interface
163