AMD-761 Datasheet, PDF (119/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions (Continued)
DDR DQS/MDAT Pad Configuration (Dev0:F1:0x8C)
Bit Name
Function
3–2 PDrvDQS
DQS P Transistor Drive Strength
These bits control the P transistor drive strength of the DQS[8:0] pins (and DM[8:0] pins)
when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at
Dev 0:F0:0x58).
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
1–0 NDrvDQS
DQS N Transistor Drive Strength
These bits control the N transistor drive strength of the DQS[8:0] pins (and DM[8:0] pins)
when any chip select is configured for x4 DIMMs in the DRAM Mode/Status register at
Dev 0:F0:0x58).
00 = Drive strength 0 (weakest)
01 = Drive strength 1
10 = Drive strength 2
11 = Drive strength 3 (strongest)
Programming Notes
Chapter 2
AMD-761™ System Controller Programmer’s Interface
107