AMD-761 Datasheet, PDF (66/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Bit Definitions (Continued)
DRAM Timing (Dev0:F0:0x54)
Bit Name
Function
11–9 t_RC
t_RC
This bit field indicates the t_RC timing value (bank cycle time: minimum time from activate
to activate of same bank).
111 = 10 cycles
110 = 9 cycles
101 = 8 cycles (recommended “safe” configuration)
100 = 7 cycles
011 = 6 cycles
010 = 5 cycles
001 = 4 cycles
000 = 3 cycles
8–7 t_RP
t_RP
This bit field indicates the t_RP timing value (precharge time: time from precharge to
activate on the same bank).
00 = 3 cycles (recommended “safe” configuration)
01 = 2 cycles
10 = 1 cycles
11 = 4 cycles
6–4 t_RAS
t_RAS
This bit field indicates the t_RAS timing value (minimum bank active time: time from activate
to precharge of same bank).
111 = 9 cycles
110 = 8 cycles
101 = 7 cycles (recommended “safe” configuration)
100 = 6 cycles
011 = 5 cycles
010 = 4 cycles
001 = 3 cycles
000 = 2 cycles
3–2 t_CL
CAS Latency of SDRAM
11 = Reserved
10 = 2.5 cycles
01 = 2 cycles (recommended “safe” configuration)
00 = 3 cycles
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AMD-761™ System Controller Programmer’s Interface
Chapter 2