AMD-761 Datasheet, PDF (143/264 Pages) Advanced Micro Devices – AMD-761-TM System Controller Software/BIOS Design Guide

24081D—February 2002
Preliminary Information
AMD-761™ System Controller Software/BIOS Design Guide
Bit Definitions
Bit Name
31–20 MLim[31:20]
19–16 Reserved
15–4 MBase[31:20]
3–0 Reserved
Programming Notes
AGP/PCI Memory Limit and Base (Dev1:0x20)
Function
Memory Limit Address
Memory limit address defines the top address of the non-prefetchable address range used
by the AGP target (graphics controller) where control registers and FIFO-like
communication interfaces are mapped. The lower 20 bits of address are assumed to be
0xFFFFF. The memory address range adheres to 1-Mbyte alignment and granularity.
Reserved
Memory Base Address
Memory Base Address defines the base address of the non-prefetchable address range
used by the AGP target (graphics controller) where control registers and FIFO-like
communication interfaces are mapped. Bits [15:4] correspond to address bits [31:20]. The
lower 20 bits of the address are assumed to be 0. The memory address range adheres to
1-Mbyte alignment and granularity.
Reserved
Chapter 2
AMD-761™ System Controller Programmer’s Interface
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